In recent years, in keeping with development of the information communication technique, there is an increasing demand for a portable device having a display unit, such as a mobile phone or a mobile information terminal. In portable devices, the sufficiently long continuous use time is of primary importance. Since the liquid crystal display device is of low power dissipation, it is widely used as a display unit for portable devices. Up to now, the liquid crystal display device was a transmitting type employing a backlight. A reflection type which does not use the backlight and which uses extraneous light has also been developed to achieve further power saving. Recently, with the tendency towards high definition display, clear picture display is required of the liquid crystal display device, such that a demand for a liquid crystal display device of an active matrix driving system, capable of clearer picture display than is possible with the conventional simple matrix system, is increasing. The demand for low power dissipation, which is made for the liquid crystal display device, is also made for its driving circuit, and researches and development of the driving circuit with low power dissipation are now going on briskly. The driving circuit for the liquid crystal display device of the active matrix driving system is hereinafter explained.
In general, the display unit of the liquid crystal display device, employing the active matrix driving system, is made up by a semiconductor substrate, including transparent pixel electrodes and thin film transistors TFTs, a counter substrate, including a sole transparent electrode over its entire surface, and the liquid crystal arranged intermediate the two substrates. A preset voltage is applied to the pixel electrodes, by controlling the TFTs, having the switching functions. The transmittance of the liquid crystal is changed by the potential difference between the pixel electrodes and the counter substrate electrode. The capacitive liquid crystal holds the potential and the transmittance for a preset time period to display the picture.
On the semiconductor substrate, there are arranged data lines for supplying plural level voltages (grayscale voltages) to be applied to the respective pixel electrodes, and scanning lines for supplying switching control signals for TFTs. The data lines operate as capacitive loads due to the capacitance of the liquid crystal sandwiched between the pixel electrodes and the counter substrate electrode and to the capacitance generated in the intersections with the respective scanning lines.
FIG. 12 schematically shows a circuit structure of a conventional typical active matrix type liquid crystal display device. Although plural pixels are provided in the display unit, only an equivalent circuit for a sole pixel is shown in FIG. 12 for simplicity. Referring to FIG. 12, one pixel is made up by a gate line 811, a data line 812, a TFT 814, a pixel electrode 815, a liquid crystal capacitance 816 and a common (counter) electrode 817. The gate line 811 is driven by a gate line driving circuit 802, while the data line 812 is driven by a data line driving circuit 803. The gate line 811 is connected in common to plural pixels forming a pixel row, while the data line 812 is connected in common to plural pixels forming a pixel column. The gate line 811 forms gate electrodes of plural TFTs of a pixel row, and the data line 812 is connected to drains or sources of plural TFTs of a pixel column. The source or drain of the TFT of a pixel is connected to a pixel electrode 815.
The grayscale voltage to the respective pixel electrodes is applied via the data line, and the grayscale voltage is written in the totality of pixels connected to the data line during one frame period (approximately 1/60 sec). Thus, the data line driving circuit has to drive the data line, as the capacitive load, with a high speed to high voltage accuracy.
That is, the data line driving circuit has to drive the data line, as the capacitive load, with a high speed, to high voltage accuracy, and is required to achieve low power dissipation for application to a portable device. As a conventional driving line driving circuit, satisfying these needs, there has been proposed a driving circuit shown for example in FIG. 13 (see for example the Patent document 1).
[Patent Document 1]
    Japanese Patent Kokai Publication JP-P2002-055659A (pages 8 to 10 and FIG. 2)
Referring to FIG. 13, this driving circuit is comprised of a preliminary charging/discharging circuit 920 and an output circuit 910. The preliminary charging/discharging circuit 920 includes a first output stage 930, having a first constant current circuit 932, performing a discharging operation, and a charging means 931, and a second output stage 940, having a second constant current circuit 942, performing a charging operation, and a discharging means 941. The charging means 931 and the discharging means 941 receive outputs of a first differential circuit 921 and a second differential circuit 922, respectively. In the driving circuit shown in FIG. 13, in driving the data line to a target voltage, the preliminary charging/discharging circuit 920 serves for driving the data line to close to the target voltage, after which the output circuit 910 drives the data line to a high accuracy.
The driving circuit shown in FIG. 13 is featured by not providing a phase compensation capacitor in order to achieve high-speed operation and low power dissipation in the preliminary charging/discharging circuit 920 of a feedback amplifier circuit. Thus, the differential circuits 921, 922 of the preliminary charging/discharging circuit 920, the first output stage 930 and the second output stage 940 are provided with respective constant current circuits, which constant current circuits control the idling current of the preliminary charging/discharging circuit 920 with the respective constant current circuits for setting the current to sufficiently small values to achieve low power dissipation. Although oscillation is liable to be produced by not providing the phase compensating capacitor, the first output stage 930 and the second output stage 940 are controlled so that, if one of the circuits is in operation, the other circuit is not in operation, with the current of the first constant current circuit 932 and the current of the second constant current circuit 942 being set to sufficiently small values to suppress oscillations to stabilize the output. Moreover, the driving circuit shown in FIG. 13 is able to operate with a high speed, with a sufficiently small idling current, by not providing the phase compensation capacitor. Moreover, if, in the driving circuit of FIG. 13, the operations of the first output stage 930 and the second output stage 940 are performed in one data period, the dynamic range can be extended to the power supply voltage range. Such extension of the dynamic range to within the power supply voltage range is equivalent to reducing the power supply voltage range, and represents efficacious means for reducing the power consumption. Thus, various other driving circuits have so far been proposed. A driving circuit shown for example in FIG. 14 has been proposed as an area saving driving circuit of a simpler structure (see for example the Patent document 2).
[Patent Document 2]
    Japanese Patent Kokai Publication JP-A-9-130171 (page 10, FIG. 5)
FIG. 14 shows a circuit configuration of an operational amplifier combined from amplifier circuits 620 and 630. Each of the amplifier circuits 620 and 630 each differentially amplifies the differential input voltage between the first and second input terminals. In FIG. 14, these amplifier circuits are shown as being of a non-inverting amplifying type voltage follower configuration for current-amplifying the input voltage Vin to output the resulting signal to an output terminal 2.
The amplifier circuit 620 is of such a structure in which p-channel current mirror circuits 621, 622 are connected as load circuits to output pairs of n-channel differential pair 623, 624, a differential portion of which is driven by a transistor 625 operating as a current source. An output stage of the amplifier circuit 620 is made up by a p-channel transistor 641, connected across the high potential power supply VDD and an output terminal 2 and a load 642 connected across a low potential power supply VSS and the output terminal 2. A connection node of the drain of the transistor 621 as an output end of the differential section and the drain of the transistor 623 is connected to the gate terminal of a p-channel transistor 641. The gate terminals of the n-channel differential pairs 623, 624 form non-inverting input ends and inverting input ends, respectively. The gate terminals of the n-channel differential pair 623, 624 are connected to an input terminal 1 and an output terminal 2. The transistor 625 and the load 642 are supplied with a bias voltage VF1.
The amplifier circuit 630 is of such a structure in which n-channel current mirror circuits 631, 632 are connected as load circuits to output pairs of p-channel differential pair 633, 634, a differential portion of which is driven by a transistor 635 operating as a current source. An output stage of the amplifier circuit 630 is made up by a n-channel transistor 651, connected across the low potential power supply VSS and the output terminal 2, and a load 652, connected across a high potential power supply VDD and the output terminal 2. A connection node of the drain of the transistor 631 as an output end of the differential section and the drain of the transistor 633 is connected to the gate terminal of a n-channel transistor 651. The gate terminals of the p-channel differential pairs 633, 634 form non-inverting input ends and inverting input ends, respectively. The gate terminals of the n-channel differential pair 633, 634 are connected to the input terminal 1 and the output terminal 2. The transistor 635 and the load 652 are supplied with a bias voltage VF2.
In an operational amplifier, shown in FIG. 14, the loads 642, 652 operate as loads having a preset resistance value, whereby the dynamic range is enlarged to within the power supply voltage range. Specifically, when the input voltage Vin is in the vicinity of the low potential power supply VSS in which the n-channel differential pairs 623, 624 are not in operation, the load 652 forms a current path across the high potential power supply VDD and the output terminal 2, so that the output terminal is driven to the voltage Vin by the operation of the amplifier circuit 630. When the input voltage Vin is in the vicinity of the high potential power supply VDD in which the p-channel differential pairs 633, 634 are not in operation, the load 642 forms a current path across the low potential power supply VSS and the output terminal 2, so that the output voltage is driven to the voltage Vin by the operation of the amplifier circuit 620.
When the input voltage Vin is in a voltage range for which both the n-channel differential pairs 623, 624 and the p-channel differential pairs 633, 634 are in operation, both the amplifier circuits 620, 630 are in operation to drive the output terminal to the voltage Vin. The operational amplifier shown in FIG. 14 enlarges the operating range to within the power supply voltage range, under the operating principle described above.
As the technique relevant to the present invention, there is known a differential amplifier used as a power supply circuit, as shown in FIG. 15 (see for example the Patent document 3).
[Patent Document 3]
    Japanese Patent Kokai Publication JP-P2001-284988A (page 7, FIG. 2)
The amplifier circuit shown in FIG. 15 is a voltage follower circuit, similar to the circuit shown in FIG. 14, and is a differential amplifier combined from an amplifier circuit 720 and an amplifier circuit 730.
The amplifier circuit 720 is of such a structure in which p-channel current mirror circuits 721, 722 are connected as load circuits to output pairs of n-channel differential pair 723, 724, a differential portion of which is driven by a constant current source 725. An output stage of the amplifier circuit 720 is made up by a p-channel transistor 711, connected across the high potential power supply VDD and the output terminal 2. A connection node of the drain of the transistor 721 as an output end of the differential section and the drain of the transistor 723 is connected to the gate terminal of a p-channel transistor 711. The gate terminals of the n-channel differential pairs 723, 724 form non-inverting input ends and inverting input ends, respectively. The gate terminal of the transistor 723 is connected to the output terminal 1, while the gate terminal of the transistor 724 is connected to the output terminal 2 via a resistor R1. A capacitance C1 is connected across the gate terminals of the transistors 724, 711.
The amplifier circuit 730 is of such a configuration in which a differential section which includes p-channel differential pair 733, 734, which is driven by a constant current source 735, and n-channel current mirror circuits 731, 732 connected as load circuits to output pairs of the p-channel differential pair 733, 734. An output stage of the amplifier circuit 730 is made up by an n-channel transistor 712, which is connected across the low potential power supply VSS and the output terminal 2. A connection node of the drain of the transistor 731 as an output node of the differential section and the drain of the transistor 733 is connected to the gate terminal of an n-channel transistor 712. The gate terminals of the p-channel differential pairs 733, 734 form non-inverting input and inverting input nodes, respectively. The gate terminal of the transistor 733 is connected to the output terminal 1, while the gate terminal of the transistor 734 is connected to the output terminal 2 via a resistor R2. A capacitance C2 is connected across the gate terminals of transistors 734, 712. The capacitors C1 and C2 of the amplifier circuits 720 and 730 and the resistors R1 and R2 are provided for phase compensation in order to stabilize the outputs of the amplifier circuits 720 and 730.
The feature of the differential amplifier shown in FIG. 15 is that the transistor pairs 723, 724 as differential pair or the transistors 733, 734 as differential pair are designed to differential capabilities such that the amplifier circuits 720 and 730 have output offsets relative to the input voltage Vin. The amplifiers are used as power supply circuits outputting the voltage Vin within the setting range of the output offset. Specifically, the device size (channel width or the gate length) between transistors forming the differential pair are changed to provide differential drain currents of the transistors of the differential pair and differential gate-to-source voltage to generate an output offset. A common input voltage VIN is applied to the amplifier circuits 720 and 730 of the differential amplifier circuit to provide for differential capabilities for the transistor pair forming the amplifier circuits 720 and 730 of the differential amplifier circuit, such that the amplifier circuits 720 of the differential amplifier circuit operates so that the first output voltage VOUT1 acts as the output voltage VOUT, and such that the amplifier circuit 730 of the differential amplifier circuit operates so that the second output voltage VOUT2 acts as the output voltage VOUT. That is, when the output offset of the amplifier circuit 720 is set so as to be positive against the voltage Vin and the output offset of the amplifier circuit 730 is set so as to be negative against the voltage Vin, the short-circuit current flowing in the transistors 711, 712 is decreased to constitute the lower supply circuit of low power dissipation.